which are also attached to many different types of devices. With different memory
devices (RAM, EPROM, EEPROM, or flash memory) at different speeds hanging on
DSP's data bus, driving the bus may become a problem. Serial converters can be
connected directly to the built-in serial ports of DSP devices. This is why many practical
DSP systems use serial ADCs and DACs.
Many applications use a single-chip device called an analog interface chip (AIC) or
coder/decoder (CODEC), which integrates an anti-aliasing filter, an ADC, a DAC, and a
reconstruction filter all on a single piece of silicon. Typical applications include modems,
speech systems, and industrial controllers. Many standards that specify the nature of the
CODEC have evolved for the purposes of switching and transmission. These devices
usually use a logarithmic quantizer, i.e., A-law or m-law, which must be converted into a
linear format for processing. The availability of inexpensive companded CODEC justi-
fies their use as front-end devices for DSP systems. DSP chips implement this format
conversion in hardware or in software by using a table lookup or calculation.
The most popular commercially available ADCs are successive approximation, dual
slope, flash, and sigma-delta. The successive-approximation ADC produces a B-bit
output in B cycles of its clock by comparing the input waveform with the output of a
digital-to-analog converter. This device uses a successive-approximation register to split
the voltage range in half in order to determine where the input signal lies. According to
the comparator result, one bit will be set or reset each time. This process proceeds
from the most significant bit (MSB) to the LSB. The successive-approximation type of
ADC is generally accurate and fast at a relatively low cost. However, its ability to follow
changes in the input signal is limited by its internal clock rate, so that it may be slow to
respond to sudden changes in the input signal.
The dual-slope ADC uses an integrator connected to the input voltage and a reference
voltage. The integrator starts at zero condition, and it is charged for a limited time. The
integrator is then switched to a known negative reference voltage and charged in the
opposite direction until it reaches zero volts again. At the same time, a digital counter
starts to record the clock cycles. The number of counts required for the integrator
output voltage to get back to zero is directly proportional to the input voltage. This
technique is very precise and can produce ADCs with high resolution. Since the
integrator is used for input and reference voltages, any small variations in temperature
and aging of components have little or no effect on these types of converters. However,
they are very slow and generally cost more than successive-approximation ADCs.
A voltage divider made by resistors is used to set reference voltages at the flash ADC
inputs. The major advantage of a flash ADC is its speed of conversion, which is simply
the propagation delay time of the comparators. Unfortunately, a B-bit ADC needs
À 1 comparators and laser-trimmed resistors. Therefore commercially available
flash ADCs usually have lower bits.
The block diagram of a sigma±delta ADC is illustrated in Figure 1.6. Sigma±delta
ADCs use a 1-bit quantizer with a very high sampling rate. Thus the requirements for an
anti-aliasing filter are significantly relaxed (i.e., the lower roll-off rate and smaller flat
response in passband). In the process of quantization, the resulting noise power is spread
evenly over the entire spectrum. As a result, the noise power within the band of interest is
lower. In order to match the output frequency with the system and increase its resolution,
a decimator is used. The advantages of the sigma±delta ADCs are high resolution and
good noise characteristics at a competitive price because they use digital filters.
INTRODUCTION TO REAL-TIME DIGITAL SIGNAL PROCESSING