amov #COEFF, XAR2
; Main data page for COEFF[4]
mov #COEFF, BSA23 ; Buffer base address is COEFF[0]
mov #0x4, BK03
; Set buffer size of 4-word
mov #2, AR2
; AR2 points to COEFF[2]
bset AR2LC
; AR2 is configured as circular pointer
mov *AR2, T0
; T0 is loaded with COEFF[2]
mov *AR2, T1
; T1 is loaded with COEFF[3]
mov *AR2, T2
; T2 is loaded with COEFF[0]
mov *AR2, T3
; T3 is loaded with COEFF[1]
Since the circular addressing uses the indirect addressing modes, the circular pointers
can be updated using the modifications listed in Table 2.4. The use of circular buffers for
FIR filtering will be introduced in Chapter 5 in details.
2.5 Pipeline and Parallelism
The pipeline technique has been widely used by many DSP manufacturers to improve
processor performance. The pipeline execution breaks a sequence of operations into
smaller segments and executes these smaller pieces in parallel. The TMS320C55x uses
the pipelining mechanism to efficiently execute its instructions to reduce the overall
execution time.
2.5.1 TMS320C55x Pipeline
Separated by the instruction buffer unit, the pipeline operation is divided into two
independent pipelines ± the program fetch pipeline and the program execution pipeline
(see Figure 2.12). The program fetch pipeline consists of the following three stages (it
uses three clock cycles):
PA (program address): The C55x instruction unit places the program address on the
program-read address bus (PAB).
PM (program memory address stable): The C55x requires one clock cycle for its
program memory address bus to be stabilized before that memory can be read.
PB (program fetch from program data bus): In this stage, four bytes of the program
code are fetched from the program memory via the 32-bit program data-read bus (PB).
Figure 2.12 The C55x pipeline execution diagram
PIPELINE AND PARALLELISM
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