Real-time digital signal processing: implementations, ... changes in the input signal is limited by its internal clock rate, so that it may be slow to
Document source : notes.ump.edu.my
Table 3.9 (continued )
j j bset
SATD
; Set Saturate bit
mov
*AR5À(#16, AC1 ; AC1 d4
j j bset
FRCT
; Set up fractional bit
mac
AC0, T0, AC1
; AC1 (d5*x c4)
j j mov
*AR5À(#16,AC0 ; AC0 d3
mac
AC1,T0, AC0
; AC0 (d5*x^2 d4*x d3)
j j mov
*AR5À(#16, AC1 ; AC1 d2
mac
AC0, T0, AC1
; AC1 (d5*x^3 d4*x^2 d3*x d2)
j j mov
*AR5À(#16, AC0 ; AC0 d1
mac
AC1, T0, AC0
; AC0 (d5*x^4 d4*x^3 d3*x^2
;
d2*x d1)
j j mov
*AR5À(#16, AC1 ; AC1 d0
macr
AC0, T0, AC1
; AC1 (d5*x^4 d4*x^3 d3*x^2 d2*x
;
d1)*x d0
j j xcc
_neg_result1, TC2
neg
AC1
_neg_result1
mov
*AR5À(#16, AC0 ; AC0 c5
j j xcc
_neg_result2, TC1
neg
AC1
_neg_result2
mov
hi(saturate(AC1(#3)), *AR0 ; Return cos(x) in Q15
;
; Start sin(x) computation
;
mov
*AR5À(#16, AC1 ; AC1 c4
mac
AC0, T0, AC1
; AC1 (c5*x c4)
j j mov
*AR5À(#16, AC0 ; AC0 c3
mac
AC1, T0, AC0
; AC0 (c5*x^2 c4*x c3)
j j mov
*AR5À(#16, AC1 ; AC1 c2
mac
AC0, T0, AC1
; AC1 (c5*x^3 c4*x^2 c3*x c2)
j j mov
*AR5À(#16, AC0 ; AC0 c1
mac
AC1, T0, AC0
; AC0 (c5*x^4 c4*x^3 c3*x^2
;
c2*x c1)
j j popboth XAR5
; Restore AR5
mpyr
T0, AC0, AC1
; AC1 (c5*x^4 c4*x^3 c3*x^2
;
c2*x c1)*x
j j xcc
_neg_result3, TC2
neg
AC1
_neg_result3
mov
hi(saturate(AC1(#3)), *AR0À
; Return sin(x)in Q15
j j bclr
FRCT
; Reset fractional bit
bclr
SATD
; Reset saturate bit
ret
.end
120
DSP FUNDAMENTALS AND IMPLEMENTATION CONSIDERATIONS
Summary :
Table 3.9 (continued ) j j bset SATD ; d1)*x d0 j j xcc _neg_result1, TC2 neg AC1 _neg_result1 mov *AR5À(#16, AC0 ; AC0 c5 j j xcc _neg_result2, TC1 neg AC1 _neg_result2 mov hi(saturate(AC1(#3)), *AR0 ;
Tags :
ar5à16,mac,bit,xcc,neg,ac1,ac0,negresult1,c3x2,hisaturateac13,c5x4,d5x4,return