e X3 and X5 module families feature high performance analog and digital ... Digital IO. Front panel 64 single-ended or 32-bit LVDS. 44 bits (J16) Cloc

www.innovative-dsp.com CompactPCI Boards c PCI-G12 Ext Clk/Ref Trigger A/D 12-bit 1 GSPS A/D 12-bit 250 kHz PLL/Clock Distribution App FPGA Xilinx Vi rt e x5 LX/SX A/D 0 Transformer Amp A/D 1 cPCI-G12 Ideal for Wireless Receiver, WLAN, WCDMA, WiMAX front end, RADAR, Medical Imaging, High Speed Data Recording, IP development Features A/D Two 1 GSPS, 12-bit A/D channels or One 2 GSPS, 12-bit A/D single channel mode +/-1V, 50 ohm, DC or AC coupled inputs D/A none Digital IO Front panel 64 single-ended or 32-bit LVDS 44 bits (J16) c PCI-COM Clock Generation App FPGA Xilinx Vi rt e x5 FX/SX SFP CAT6 Cu to 1Gbps Fiber to 4.125 Gbps SFP CAT6 Cu to 1Gbps Fiber to 4.125 Gbps SFP CAT6 Cu to 1Gbps Fiber to 4.125 Gbps SFP CAT6 Cu to 1Gbps Fiber to 4.125 Gbps Rocket IO Rocket IO Rocket IO Rocket IO cPCI-COM Front end signal processing ideal node for remote IO and distributed processing systems such Remote Radio Head (RRH) applications Features Front Panel IO Interface Up to 3.125 Gbps D/A none Digital IO 16-bits (J16) c PCI-400m Ext Clk Tr iggers [1..0] A/D 14-bit 400 MSPS DAC 16-bit 500 MSPS App FPGA Xilinx Vi rt ex5 LX/SX MUX Crystal cPCI-400M Ideal for Wireless Receiver/Transmitter, WLAN, WCDMA, WiMAX front end, RADAR, ECM, Electronic Warfare, High Speed Data Recording and Playback, High Speed Servo Controls, Spectral Analysis, IP development Features A/D D/A Digital IO 33-bits (J16) IP Cores for SDR c PCI-210m Ext Clk Tr igger App FPGA Xilinx Vi rt e x5 LX/SX A/D 14-bit 250 MSPS A/D 14-bit 250 MSPS A/D 14-bit 250 MSPS A/D 14-bit 250 MSPS MUX Crystal cPCI-210M Ideal for Wireless Receiver WLAN, WCDMA, WiMAX front end, RADAR, ECM, Electronic Warfare, High Speed Data Recording, Spectral Analysis, IP development Features A/D SMA inputs D/A none Digital IO 16-bits (J16) IP Cores for SDR 16-4096 DDC channels