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This document is a cache from http://www.entegra.co.uk/pdfs/2009_Catalog_FINAL_eBook.pdf


e X3 and X5 module families feature high performance analog and digital ... Digital IO. Front panel 64 single-ended or 32-bit LVDS. 44 bits (J16) Cloc

Document source : www.entegra.co.uk


30
Innovative Integration | 805.578.4260 | www.innovative-dsp.com
PCI Boards
Application-Oriented Performance
64-bit PCI, Floating Point DSP, Integrated I/O
High roughput & Processing Bandwidth
Texas Instruments TMS320C6711 &
TMS320C6713 DSPs

Integrated Analog I/O; Flexible Trigger;
Mechanisms built-in; DDS clock on board
Digital Gain/Offset correction

External Clock and Trigger Input
Multi-board Synchronization
External Data FIFOPort >50MB/s

Integrated in TI's Code Composer Studio
Powerful examples with source code
DSP/BIOS Drivers; C/C++; Host-Side Libraries
Benefit
Performance; Easy development; Fast execution; Floating point DSP; C-Code friendly; High dynamic range;
Simple memory map

Best connectivity for high rate, low latency; Easily configure any capture mode;
Ultra-fine resolution timebase; In system calibration, no pots tweaking


Synchronize with external events
Simple system scale-up
Private data link to external hardware

Standard, portable; Can use 3rd party code; Accelerate application development
Higher Performance, Simple I/O control; Simplify usage of complex DSP resources
Fast setup of data view/process/log
Matador Series Features
Application-Oriented Performance
e Matador Series o ers a full range of performance-
oriented DSP boards which employ an advanced, ma-
ture design. We have carefully designed this product
family around the advanced, but mature, TI C6711 &
C6713 DSPs and Xilinx Virtex and Spartan FPGAs.
Ready for application deployment, the Matador family
integrates state-of-art components, circuit architecture,
logic design and so ware tools to provide real-time so-
lutions in all leading edge elds.
Del n
Del n employs the highest quality analog circuitry to
deliver an exceptional S/N performance exceeding 100
dB in SFDR and hosts 32 simultaneous A/Ds and 6 D/
As, at 24-bit.
P25M
Featuring the C6713 oating point DSP a 1M gate Spar-
tan3 FPGA, P25M provides (4) 25MSPS, 16-bit A/Ds
and (4) 50MSPS, 16-bit D/As. All facets of system de-
velopment are greatly accelerated with P25M's full-fea-
tured DSP programming tools and FrameWork Logic
development package including MATLAB BSP.
Toro
Toro features 16 simultaneous A/Ds and D/As, both at 16-bit at up to 250kHz, using the highest quality analog circuitry to deliver exceptional S/N performance.
Toro is the perfect solution for applications like advance servo-control, MIMO systems, MEMS and optical switch control, vibration analysis and precision
instruments.
ext digital clock
Auto Cal. Switch
w/Ref. Voltage
JTAG
Debug Port
Clock to 300 MHz
User Reconfiguration (option)
32-bit Digital I/O
A/D Start Trigger
A/D Stop Trigger
D/A Start Trigger
D/A Stop Trigger
Card Specific A/D Inputs
Card Specific D/A Outputs
32-bit Digital I/O
IDC 40
FIFOPort
54 Pin
Header
External Clock
SMB
External INT
SMB
IDC 14
ext digital clock
Brack
et C
onnec
to
r
TMS320C6713 DSP
32-bit floating point
SDRAM
32 MB
DDS
0-25MHz
.02 Hz step
(2) 32-bit
Timers (1:4)
(8) Parallel
Execution Units
L2 Cache
64 KB
L1 Program
Cache 4 KB
(16)+1 EDMA
Channels
L1 Data
Cache 4 KB
(5) Serial
Ports
Analog Control
Xilinx FPGA
Gain/Offset
Correction
A/D
FIFO
Gain/Offset
Correction
FIFO
Trigger Control
Event Logging
D/A
FIFO
EMIF
HPI
Xilinx FPGA
Host PCI Bus
64/32 bit, 3.3/5V, 33MHz
264MB/s / 132MB/s
Time Base
Selection Matrix
Mailbox
Messaging I/O
PCI Control
PCI FIFO
Multi-board synchronization
SyncLink/ClkLink







Summary :

Voltage JTAG Debug Port Clock to 300 MHz User Reconfiguration (option) 32-bit Digital I/O A/D Start Trigger A/D Stop Trigger D/A Start Trigger D/A Stop Trigger Card Specific A/D Inputs Card Specific D/A Outputs 32-bit Digital I/O IDC 40 FIFOPort 54 Pin Header External Clock SMB External INT SMB IDC 14 ext digital clock Brack et C onnec to r TMS320C6713 DSP 32-bit floating point SDRAM 32 MB DDS 0-25MHz .02 Hz step (2) 32-bit Timers (1:4) (8) Parallel Execution Units L2 Cache 64 KB L1 Program Cache 4 KB (16)+1 EDMA Channels L1 Data Cache 4 KB (5) Serial Ports Analog Control Xilinx FPGA Gain/Offset Correction A/D FIFO Gain/Offset Correction FIFO Trigger Control Event Logging D/A FIFO EMIF HPI Xilinx FPGA Host PCI Bus 64/32 bit, 3.3/5V, 33MHz 264MB/s / 132MB/s Time Base Selection Matrix Mailbox Messaging I/O PCI Control PCI FIFO Multi-board synchronization SyncLink/ClkLink


Tags : dsp,trigger,performance,external,clock,digital,pci,control,fifo,32bit,point,data,analog





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