S3C6410_CIRCUIT DESIGN GUIDE REV 1.00
36. IIS BUS CONTROLLER
36.1 Signal Description
Signal
Input(I)/Output(O)
Function
Description
XpcmDCLK[0] Xi2sCLK[0]
XpcmDCLK[1]
I/O
Xi2sCLK[1]
IIS-bus serial clock
XpcmEXTCLK[0] Xi2sCDCLK[0]
XpcmEXTCLK[1]
I/O
Xi2sCDCLK[1]
IIS CODEC system clock
XpcmFSYNC[0] Xi2sLRCK[0]
XpcmFSYNC[1]
I/O
Xi2sLRCK[1]
IIS-bus channel select clock
XpcmSIN[0] Xi2sSI[0]
XpcmSIN[1]
I
Xi2sSI[1]
IIS-bus serial data input
XpcmSOUT[0] Xi2sSO[0]
XpcmSOUT[1]
O
Xi2sSO[1]
IIS-bus serial data output
36.2 Audio Port
There are two IIS Interface Controllers in S3C6410X. Each Controller has a port to accept and drive signals
external codec. Controller 0 uses Audio Port 0 (Port D), and Controller 1 uses Audio Port 1 (Port 1).
36.3 External Clock Source
S3C6410X provides a master clock to the codec through the Xi2sCDCLK line. This configuration has an
advantage that it is not necessary to configure oscillator circuit. For the making Master Clock, S3C6410X uses
and divides EPLL, MPLL or PCLK (refer to the User's Manual). If an oscillator circuit is configured for a precise
clock for the Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as
a source of master clock through the Xi2sCDCLK line.
36.4 Connection Example
Figure 66_1) IIS Connection Example with WM8753 (Master Mode)
90
Summary :
IIS BUS CONTROLLER 36.1 Signal Description Signal Input(I)/Output(O) Function Description XpcmDCLK[0] Xi2sCLK[0] XpcmDCLK[1] I/O Xi2sCLK[1] IIS-bus serial clock XpcmEXTCLK[0] Xi2sCDCLK[0] XpcmEXTCLK[1] I/O Xi2sCDCLK[1] IIS CODEC system clock XpcmFSYNC[0] Xi2sLRCK[0] XpcmFSYNC[1] I/O Xi2sLRCK[1] IIS-bus channel select clock XpcmSIN[0] Xi2sSI[0] XpcmSIN[1] I Xi2sSI[1] IIS-bus serial data input XpcmSOUT[0] Xi2sSO[0] XpcmSOUT[1] O Xi2sSO[1] IIS-bus serial data output 36.2 Audio Port There are two IIS Interface Controllers in S3C6410X.
Tags :
clock,port,iisbus,iis,master,controller,codec,audio,serial,s3c6410x,uses,oscillator,connection