Cadence Mixed-Signal Circuit Design Environment User Guide
The Mixed-Signal Interface
October 2003
18
Product Version 5.0
In OpenAccess, there is only one mixed-signal interface to the Cadence Spectre analog
simulator - SpectreVerilog, which uses direct simulation.
The simulators send output to the simulation output database.
Design Details
The mixed-signal simulator requires some design details:
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You must partition the circuit into analog and digital sections before running the
simulation.
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The design must contain at least one analog component or the circuit simulator will not
run. (You can use an inactive analog component in the design.)
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The design must contain at least one digital component or the logic simulator will not run.
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You must have at least one interface net.
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Interface elements cannot be bidirectional.
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Digital-to-analog interface elements can generate high impedance states. Analog-to-
digital interface elements do not generate high impedance states.
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Analog stimuli defined in the analog stimulus file cannot be used to drive a digital net.
However, structural analog stimulus instances in the schematic can drive digital
components through interface nets.
Cadence Mixed-Signal Interactive Simulation
Environment
Analog Circuit
Simulator
Verilog Logic
Simulator
Simulation Output Database
IPC
Summary :
Cadence Mixed-Signal Circuit Design Environment User Guide The Mixed-Signal Interface October 2003 18 Product Version 5.0 In OpenAccess, there is only one mixed-signal interface to the Cadence Spectre analog simulator - SpectreVerilog, which uses direct simulation.
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