Cadence Mixed-Signal Circuit Design Environment User Guide
The Mixed-Signal Interface
October 2003
28
Product Version 5.0
The following table describes CDF parameters of A2AO IE macro models.
IE Selection Rules
There are two modes for generating interface elements: detailed and nondetailed.
Flat netlisting (FNL) supports both detailed and nondetailed IE generation. Hierarchical
netlisting (HNL) supports only nondetailed IE generation. For SpectreVerilog simulation, only
HNL is available.
Detailed IE Generation
In detailed IE generation mode, each digital pin connected to an interface net generates an
interface element. There can be more than one IE at an interface net. For more information
on the detailed IE generation mode, see "Flat Netlisting" on page 132.
Caution
In OpenAccess, mixed socket netlisting and simulation are not
supported. Therefore, FNL and detailed IE generation are also not
supported.
a2aI_abs
Absolute tolerance. (Not used.)
a2aI_deltat
Minimum delta time between events. (Not used.)
a2aI_ron
Output resistance.
Parameter
Description
macro
Macro model (subcircuit) filename that the analog simulator uses for the
IE macro model. You must specify a model library or model path (from the
Setup menu) to indicate to the simulator how to access the macro model
files.
a2aO_rel
Relative tolerance.
a2aO_abs
Absolute tolerance.
a2aO_deltat
Minimum delta time between events.
Parameter
Description
Summary :
Cadence Mixed-Signal Circuit Design Environment User Guide The Mixed-Signal Interface October 2003 28 Product Version 5.0 The following table describes CDF parameters of A2AO IE macro models. Detailed IE Generation In detailed IE generation mode, each digital pin connected to an interface net generates an interface element.
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detailed,generation,interface,macro,model,netlisting,tolerance,nondetailed,simulator,hnl,between,fnl,parameter