Cadence Mixed-Signal Circuit Design Environment User Guide
Interface Element Macro Models
Product Version 5.0
.A2D DIGITAL_DEST SENSE_TERM A2D_V0 A2D_V1 A2D_TX NESTLEV
Note: When building the IE model file, be sure to set the
parameter of the IE
primitive correctly. Do not use the
parameter in the component description format
(CDF) for an IE macro model cell.
The cdsSpice A2D primitive is implemented like a grounded voltmeter (the equivalent of an
open circuit). The primitive senses the voltage at its
relative to ground.
When the voltage is below
, the A2D primitive sends a logic 0 to the digital destination
When the voltage is above
, the primitive sends a logic 1 to the digital destination.
When the voltage stays between
for a time longer than
primitive sends a logic X.
Note: There is no translation from a voltage to the high-impedance (Z) state.
The foreign simulator's name for the destination of the A2D signal
(Verilog import name).
The sensing terminal. This terminal should usually be connected
to the original interface net.
The low voltage threshold. Voltages below this will be logical 0.
The high voltage threshold. Voltages above this will be logical 1.
Length of time that the voltage can stay between
before logical X is declared.
Specifies the subcircuit nesting level of the interface primitive. The
default value is 0 (the primitive is not nested inside the subcircuit
of an interface element model file).