Cadence Mixed-Signal Circuit Design Environment User Guide
Interface Element Macro Models
October 2003
36
Product Version 5.0
.A2D DIGITAL_DEST SENSE_TERM A2D_V0 A2D_V1 A2D_TX NESTLEV
Note: When building the IE model file, be sure to set the
NESTLEV
parameter of the IE
primitive correctly. Do not use the
NESTLEV
parameter in the component description format
(CDF) for an IE macro model cell.
The cdsSpice A2D primitive is implemented like a grounded voltmeter (the equivalent of an
open circuit). The primitive senses the voltage at its
SENSE_TERM
relative to ground.
When the voltage is below
A2D_V0
, the A2D primitive sends a logic 0 to the digital destination
DIGITAL_DEST
.
When the voltage is above
A2D_V1
, the primitive sends a logic 1 to the digital destination.
When the voltage stays between
A2D_V0
and
A2D_V1
for a time longer than
A2D_TX
, the
primitive sends a logic X.
Note: There is no translation from a voltage to the high-impedance (Z) state.
Parameter
Description
DIGITAL_DEST
The foreign simulator's name for the destination of the A2D signal
(Verilog import name).
SENSE_TERM
The sensing terminal. This terminal should usually be connected
to the original interface net.
A2D_V0
The low voltage threshold. Voltages below this will be logical 0.
A2D_V1
The high voltage threshold. Voltages above this will be logical 1.
A2D_TX
Length of time that the voltage can stay between
A2D_V0
and
A2D_V1
before logical X is declared.
NESTLEV
Specifies the subcircuit nesting level of the interface primitive. The
default value is 0 (the primitive is not nested inside the subcircuit
of an interface element model file).