Cadence Mixed-Signal Circuit Design Environment User Guide
Interface Element Macro Models
October 2003
55
Product Version 5.0
.D2A DIGITAL_SRC VBCV D2A_VL D2A_VH D2A_TR D2A_TF NESTLEV
VBCV POSITIVE_TERM NEGATIVE_TERM PWL 0 0
The cdsSpice D2A primitive is implemented like a piece-wise linear voltage source (PWLVS),
also called a Boolean-controlled voltage source (BCV), with zero output resistance.
When the digital source changes to logic 1, the D2A PWLVS ramps from its current value to
D2A_VH
within
D2A_TR
time.
When the digital source changes to logic 0, the D2A PWLVS ramps from its current value to
D2A_VL
within
D2A_TF
time.
When the digital source changes to logic Z, the D2A PWLVS ramps to the average of
D2A_VL
and
D2A_VH
using either
D2A_TR
/2 time or
D2A_TF
/2 time.
When the digital source changes to logic X, the D2A PWLVS stays at its current value, and a
warning is generated.
Parameter
Description
DIGITAL_SRC
Foreign simulator's name for the source of the D2A signal (Verilog
®
export name).
VBCV
Name of the piece-wise linear source generating the analog
voltage. The name must match on both lines of the primitive.
D2A_VL
Final voltage value corresponding to logical 0.
D2AVH
Final voltage value corresponding to logical 1.
D2A_TR
Time for rising transition from
D2A_VL
to
D2A_VH
.
D2A_TF
Time for falling transition from
D2A_VH
to
D2A_VL
.
NESTLEV
Specifies the nesting level of the interface primitive. The default
value is 0.