Cadence Mixed-Signal Circuit Design Environment User Guide
Interface Element Macro Models
Product Version 5.0
There are implementation differences between Spectre and SPICE simulation. The Spectre
interface primitive is different from the SPICE interface primitive. Some other circuit primitives
might be supported by the Spectre simulator but not in the SPICE simulator, or conversely.
To build a SpectreS interface model, therefore, you need to replace the SPICE-compatible
D2A interface primitive with the Spectre D2A interface primitive, and use only circuit devices
that are supported by the Spectre simulator in the macro model file.
The Spectre D2A interface primitive is a two-terminal device with the following syntax and
Name positiveTerm negativeTerm parameter=value ...
The Spectre D2A primitive is implemented like a piece-wise linear voltage source (PWLVS)
with an output resistance
When the digital source changes to logic 1, the D2A PWLVS ramps from its current value to
When the digital source changes to logic 0, the D2A PWLVS ramps from its current value to
When the digital source changes to logic Z, the D2A PWLVS ramps to the average of
When the digital source changes to logic X, the D2A PWLVS stays at its current value, and a
warning is generated.
control the value of the PWLVS. The actual
depends on the resistance
loading of circuitry connected to the D2A primitive.
Foreign simulator's name for the source of the D2A signal (Verilog
Final value for logical 0. Default is 0 V.
Final value for logical 1. Default is 5 V.
Time for transition from val0 to val1. Default is 1 ns.
Time for transition from val1 to val0. Default is 1 ns.
Output resistance of the D2A primitive. Default is 100 Ohm.
Nesting level of the interface primitive. The default value is 0.