Cadence Mixed-Signal Circuit Design Environment User Guide
Interface Element Macro Models
October 2003
71
Product Version 5.0
The level 1 interface element, SpectreS MOS1_d2a, is a macro with the following parameters:
The interface primitive
da&1
translates the logic state and drives an intermediate node
&1
.
The resistor
R&1
models the impedance of the digital output pin and connects
da&1
to the
interface net
&2
. Parameter
&1
represents both the Verilog import name and the intermediate
node.
MOS2_d2a
The level 2 interface element, MOS2_d2a, has a pull-up switch and a pull-down switch to
model independent sourcing, sinking, and tri-state capabilities of the digital output pin.
Macro file
MOS2_d2a.S
:
da&1 &1 0 d2a src="&1" val0=&3 val1=&4 rise=&5 fall=&6
X&1 &1 &2 C&1
.SUBCKT C&1 1 2
VDD 3 0 &4
VSS 4 0 &3
C1 2 0 0.1P
W1 3 2 1 0 relay vt1=&7 vt2=&7+1e-6 ropen=1e+12 rclosed=&9
W2 4 2 1 0 relay vt1=&8 vt2=&8-1e-6 ropen=1e+12 rclosed=&10
.ENDS C&1
The following parameters are mapped in order:
Macro
Parameter
Mnemonic Parameter Name
&1
Digital source, intermediate node
&2
Analog node (interface net)
&3
D2A_VL
&4
D2A_VH
&5
D2A_TR
&6
D2A_TF
&7
D2A_ROUT
Macro
Parameter
Mnemonic Parameter Name
&1
Digital source, intermediate node
&2
Analog node (interface net)
Summary :
val0=&3 val1=&4 rise=&5 fall=&6 X&1 &1 &2 C&1 .SUBCKT C&1 1 2 VDD 3 0 &4 VSS 4 0 &3 C1 2 0 0.1P W1 3 2 1 0 relay vt1=&7 vt2=&7+1e-6 ropen=1e+12 rclosed=&9 W2 4 2 1 0 relay vt1=&8 vt2=&8-1e-6 ropen=1e+12 rclosed=&10 .ENDS C&1 The following parameters are mapped in order: Macro Parameter Mnemonic Parameter Name &1 Digital source, intermediate node &2 Analog node (interface net) &3 D2A_VL &4 D2A_VH &5 D2A_TR &6 D2A_TF &7 D2A_ROUT Macro Parameter Mnemonic Parameter Name &1 Digital source, intermediate node &2 Analog node (interface net)
Tags :
interface,amp1,node,parameter,macro,digital,amp2,intermediate,camp1,daamp1,element,name,net