Cadence Mixed-Signal Circuit Design Environment User Guide
Partitioning Your Design
October 2003
95
Product Version 5.0
The following figure illustrates how hierarchy expansion is performed on a simple design. The
solid lines show the selected views and design expansion based on the view list and stop list
provided in the figure. This is comparable to the expansion conducted by the HED, based on
its global view list and stop list.
By using instance binding, the verilog view is specified as the view to use for inv2.
This overrides the default binding to the schematic view. Because verilog is in the stop list, no
further expansion is performed.
symbol
symbol
symbol
nmos
pmos
spectre
spectre
schematic
View list:
Stop list:
spectre schematic cmos.sch verilog
spectre verilog
Top cell
inv2
inv1
verilog
symbol
symbol
symbol
nmos
pmos
spectre
spectre
schematic
verilog
Summary :
symbol symbol symbol nmos pmos spectre spectre schematic View list: Stop list: spectre schematic cmos.sch verilog spectre verilog Top cell inv2 inv1 verilog symbol symbol symbol nmos pmos spectre spectre schematic verilog
Tags :
list,iew,erilog,spectre,symbol,expansion,stop,design,schematic,binding,performed,figure,pmos