Cadence Mixed-Signal Circuit Design Environment User Guide
October 2003
109
Product Version 5.0
5
Netlisting Options
Both hierarchical netlisting (HNL) and flat netlisting (FNL) are available in the front-end mixed-
signal simulation flow and in the mixed-signal parasitic simulation (MSPS) flow. (For more
information on parasitic simulation, see the Cadence® Parasitic Simulation User Guide.)
Because HNL offers many advantages over FNL (which are described in "Differences
between HNL and FNL" on page 110), we recommend that you use HNL unless you require
features that are only available in FNL.
Note: In OpenAccess, mixed socket netlisting and simulation are not supported, and
therefore, FNL and detailed IE generation are also not supported.
Verilog Netlisting Options
Choosing Setup Environment from the Simulation window opens the Environment
Options form. Depending on whether the Mixed Signal Netlisting Mode setting on this form
is Flat or Hierarchical, clicking the Verilog Netlist Option button at the bottom of the form
opens either the Verilog HNL Netlisting Options form or the Verilog FNL Netlisting Options
form.
The Verilog
®
netlisting options include settings such as
s
Global Power Nets and Global Ground Nets
s
Netlist SwitchRC, Mixed HNL, Skip Null Port, and Netlist Explicitly (for Verilog FNL)
s
Generate Test Fixture Template, Netlist Uppercase, Netlist SwitchRC, Support
VhdlImport, Global TimeScale Overwrite, Global Sim Time, Global Sim Precision
and many others (for Verilog HNL)
For more information about these options, see the Verilog-XL Integration for Composer
Reference.
The default settings in these forms are the default Verilog netlisting options used in the
Verilog-XL Integration for Composer tool. If you change any settings, you can save them by
saving the state of the mixed-signal design environment (by choosing Session Save State
from the Simulation window and providing a file name). To load the settings in a later session,