Cadence Mixed-Signal Circuit Design Environment User Guide
Product Version 5.0
In OpenAccess, nlpExpr and ilExpr are not supported.
For digital HNL, the mixed-signal design environment implements the same parameter
specification and passing conventions as for Verilog integration because the same Verilog
HNL netlister is used. For information on parameter specification format, refer to the Verilog-
XL Integration for Composer User Guide.
For a description of how parameters are passed in the hierarchy of a mixed-signal design,
see "Setting Design Variables and Parameters" on page 91.
Stop View List Specification
The HNL netlisting algorithm does not expand cellviews containing internal hierarchy; it
preserves the design hierarchy containing text cellviews. To indicate a primitive text cellview
that has no internal hierarchy, the
property is set to
automatically by a
language analyzer (such as the SpectreHDL editor). HNL identifies which text cellviews are
primitive cellviews and which text cellviews contain internal hierarchy by examining the
property on each cellview.
To use HNL in an analog-only design or a mixed-signal design
Remove behavioral text views such as behavioral, functional, ahdl, and veriloga from
the HED stop view list so that HNL will traverse non-primitive text cellviews.
Explicit Netlisting (Digital)
With explicit netlisting, the digital netlist contains explicit instance terminals and signal
connections, such as
modName instName (.instTermName1(netName1),
modName instName (netName1, netName2, ...)
Note: Verilog-XL built-in primitives are not netlisted explicitly because the terminals of these
primitives do not have any names.
To specify explicit netlisting in Verilog HNL
1. In the Simulation window, choose Setup Environment to display the Environment