Cadence Mixed-Signal Circuit Design Environment User Guide
Netlisting Options
October 2003
120
Product Version 5.0
Bus Handling
IE generation can occur at bus nets. Part of the bus can be analog, digital, or mixed.
module block( );
...
wire [1:0] I;
wire [1:0] C;
reg mixedNet99999;
assign I[0] = mixedNet99999;
...
endModule
$vmx_define_import(test.top.mixedNet99999, "99999"); // /I<0>
$vmx_define_export(test.top.C[0], "99999"); // /C<0>
HNL Testfixture File
The HNL
testfixture.template
file is automatically generated at netlisting. It includes
the digital stimulus from a separate file
testfixture.verimix
. This ensures the
stimulus file is not overwritten.
The following sample shows an HNL
testfixture.template
file.
`timescale 1ns / 1ns
module test;
wire out;
integer dc_mode_flag;
integer output_change_count;
inv0:1
test
block/top
C0:1
C0
C1
I0:1
I0
Summary :
Cadence Mixed-Signal Circuit Design Environment User Guide Netlisting Options October 2003 120 Product Version 5.0 Bus Handling IE generation can occur at bus nets.
Tags :
file,hnl,wire,bus,integer,digital,netlisting,stimulus,quot99999quot,1ns,module,test,mixednet99999