Cadence Mixed-Signal Circuit Design Environment User Guide
Netlisting Options
October 2003
130
Product Version 5.0
// Library - mhnlTestLib, Cell - hierTwoRItop, View - schematic
// LAST TIME SAVED: Nov 6 16:18:32 1996
// NETLIST TIME: Nov 6 16:23:11 1996
`timescale 1ns / 1ns
module hierTwoRItop ( out, out1, in1, in2 );
output out, out1;
input in1, in2;
specify
specparam CDS_LIBNAME = "mhnlTestLib";
specparam CDS_CELLNAME = "hierTwoRItop";
specparam CDS_VIEWNAME = "schematic";
endspecify
resInvBuf I32 ( .in(in2), .out(out1));
resInvBuf I31 ( .in(in1), .out(out));
endmodule
// Begin Interface Element Header
// and Verimix Synchronization task
initial begin
$vmx_initialize( "spectre", dc_mode_flag);
$vmx_define_export( test.top.I32.nd2a,
"xi32/99999"); // /I32/nd2a
$vmx_define_import( test.top.I32.mixedNet99998,
"xi32/99998"); // /I32/na2d
$vmx_define_export( test.top.I31.nd2a,
"xi31/99999"); // /I31/nd2a
$vmx_define_import( test.top.I31.mixedNet99998,
"xi31/99998"); // /I31/na2d
$vmx_end_definition;
Begins flattened IE
definitions