Cadence Mixed-Signal Circuit Design Environment User Guide
Netlisting Options
October 2003
131
Product Version 5.0
Inherited Connections in the Netlist
The pseudo connections that the partitioner creates to resolve inherited connections appear
in the resulting netlist, renamed as signals with the prefix
inh_
. The name mapping is
specified in a comment. The renaming is needed to conform to requirements of the simulation
language. A portion of an example netlist is shown here:
vmx_time_offset = 0;
max_dc_iter = 0;
dc_mode_flag = 1;
$vmx_start_sim("spectre");
dc_iterations = 0;
while(dc_mode_flag != 0)
begin
#0 $vmx_do_dc("spectre",
output_change_count);
dc_iterations = (dc_iterations + 1);
if( (output_change_count == 0) ||
(dc_iterations >= max_dc_iter) )
begin
dc_mode_flag = 0;
vmx_time_offset = $time;
end
end
end
// End Interface Element Footer
// and Verimix Synchronization task
// Begin WSF Save Waveforms
initial begin
$save_waveform( "binary"
,"/I31/mid", test.top.I31.mid
,"/I32/mid", test.top.I32.mid
);
end
// End WSF Save Waveforms
Initializes DC time offset
Tells Spectre to start
simulation
Sets maximum number
of DC iterations
Finds DC solution
Begins DC loop
between Spectre and
Verilog
Sets DC time offset
Summary :
end // End WSF Save Waveforms Initializes DC time offset Tells Spectre to start simulation Sets maximum number of DC iterations Finds DC solution Begins DC loop between Spectre and Verilog Sets DC time offset
Tags :
end,begin,dciterations,time,connections,netlist,outputchangecount,offset,maxdciter,spectre,sets,dcmodeflag,mxtimeoffset