Cadence Mixed-Signal Circuit Design Environment User Guide
Product Version 5.0
specified on the primitive instance containing the Verilog hierarchical property or on any
parent instance of that primitive instance.
The NLP expression property in the Verilog hierarchical property specifies a search name.
The Verilog FNL netlister searches for a property name that matches the value of the NLP
expression. The search starts with the instance, proceeds to the parent instance, then the
grandparent instance, and on through all ancestral instances, stopping at the youngest
ancestral instance that contains the property name. The value of the property matching the
search is substituted for the
property and formatted in the
For example, given the following design:
Cell paramTestBottom has instance I1 of cell inv1. Instance I1 has
property I1~>verilog~>expr of type NLPExpr.
Cell paramTest1Up has instances I0, I1, I3 of cell paramTestBottom.
Instance I0 has no property. Instance I1 has property I1~>expr =
inst1In1Up. Instance I3 has property I3~>expr =
[@expr1:%:defaultExpr1] of type NLPExpr.
Cell paramTestTop has instances I0 and I1 of cell paramTest1Up.
Instance I0 has property I0~>expr = inst0InTopCell and I0~>expr1 =
expr1ValOfInst0InTopCell. Instance I1 has property I1~>expr =
the Verilog netlist appears as follows:
inv1 #20 I0( N5, N9 ); // /I0/I3/I1
I0.expr = "expr1ValOfInst0InTopCell";
inv1 #20 I2( N4, N15 ); // /I0/I1/I1
I2.expr = "inst1In1Up";
inv1 #20 I4( N8, N21 ); // /I0/I0/I1
I4.expr = "inst0InTopCell";
inv1 #20 I6( N27, N31 ); // /I1/I3/I1
I6.expr = "defaultExpr1";
inv1 #20 I8( N2, N37 ); // /I1/I1/I1
I8.expr = "inst1In1Up";
inv1 #20 I10( N30, N43 ); // /I1/I0/I1
I10.expr = "inst1InTopCell";