Cadence Mixed-Signal Circuit Design Environment User Guide
Netlisting Options
October 2003
141
Product Version 5.0
//Defines registers.
reg [#/in_ref];
//Instantiates top block.
top top([#/feed_back],[#/in_ref]);
//Starts initial block.
//Commands are executed once
//at the beginning of each simulation.
initial
begin
//Monitors wires during simulation.
$monitor("%d in_ref=%b feed_back=%b up=%b
down=%b", $time, top.[#/in_ref],
top.[#/feed_back], top.[#/up],
top.[#/down];
//Forces nets during circuit initialization.
force top.[#/in_ref] = 0;/* net in_ref */
force top.[#/feed_back] = 0;/* net feed_back */
force top.[#/out2] = 1;/* net out2 */
force top.[#/out4] = 0;/* net out4 */
force top.[#/out5] = 0;/* net out5 */
force top.[#/out9] = 1;/* net out9 */
//Releases forced nets after 620 time units.
#620 release top.[#/feed_back];
release top.[#/out2];
release top.[#/out4];
release top.[#/out5];
release top.[#/out9];
//Ends initial block.
Flat Netlist Files
Mixed-signal software creates a number of netlist files and directories in processing flat
netlists. For descriptions of these files and directories, see the appropriate category below.
Sample analog and digital flat netlists are also provided.
The final digital netlist--called
final
--is used by the Verilog simulator. The file is in flattened
form, containing only primitive digital instances.
To display the final digital netlist
From the Simulation window, choose Simulation Netlist Create Final.
The final analog netlist is in flattened form, containing only primitive analog instances. This
file is used by the circuit simulator. You can also use this file to run mixed-signal simulation
outside of the mixed-signal circuit design environment. The final analog netlist file resides in