Cadence Mixed-Signal Circuit Design Environment User Guide
October 2003
153
Product Version 5.0
6
Running a Mixed-Signal Simulation
As with any simulation, a mixed-signal simulation involves a number of setup and processing
steps. These are discussed in this chapter.
s
Setting Simulator Options
s
Input Stimulus for FNL
s
Input Stimulus for HNL
s
Setting Design Variables
s
Choosing Analyses
s
Running the Simulation
s
Control and Debugging
s
Viewing and Analyzing Simulation Output
During simulation, if you are using one of the mixed-signal socket simulators, you can
interactively control and debug both AHDL and Verilog
®
modules.
The SpectreVerilog simulator does not support the direct simulation non-batch control feature
because of which you cannot interactively control and debug both AHDL and Verilog
®
modules.
In CDBA, there are four mixed-signal interfaces to the Analog Design Environment:
SpectreSVerilog, hspiceSVerilog, cdsSpiceVerilog (which use socket simulation) and
SpectreVerilog (which uses direct simulation).
In OpenAccess, there is only one mixed-signal interface to the Analog Design Environment-
SpectreVerilog, which uses direct simulation.
Once the design is simulated satisfactorily, you can probe the layout and schematic views to
determine specific characteristics of the design. Typically, your design will require numerous
iterations where design details are modified and the design is resimulated until the results are
acceptable.
Summary :
Cadence Mixed-Signal Circuit Design Environment User Guide October 2003 153 Product Version 5.0 6 Running a Mixed-Signal Simulation As with any simulation, a mixed-signal simulation involves a number of setup and processing steps.
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