Cadence Mixed-Signal Circuit Design Environment User Guide
Running a Mixed-Signal Simulation
Product Version 5.0
3. Copy the stimulus portion of the former
file from the file in
which it was saved.
4. Make changes as needed to the new file displayed in the editing window.
5. Save the new
file and close the editor.
The following example shows a flat
stimulus file for Verilog FNL.
`timescale 100ps / 100ps
//Begins test module definition.
//Instantiates top block.
//Starts initial block.
//Commands are executed once
//at the beginning of each simulation.
//Monitors wires during simulation.
$monitor("%d in_ref=%b feed_back=%b up=%b
down=%b", $time, top.[#/in_ref],
//Forces nets during circuit initialization.
force top.[#/in_ref] = 0;/* net in_ref */
force top.[#/feed_back] = 0;/* net feed_back */
force top.[#/out2] = 1;/* net out2 */
force top.[#/out4] = 0;/* net out4 */
force top.[#/out5] = 0;/* net out5 */
force top.[#/out9] = 1;/* net out9 */
//Releases forced nets after 620 time units.
#620 release top.[#/feed_back];
//Ends initial block.