Cadence Mixed-Signal Circuit Design Environment User Guide
Running a Mixed-Signal Simulation
October 2003
174
Product Version 5.0
end
initial begin
#2418 tx[3] = 1'b1;
#17 tx[3] = 1'b0;
end
initial begin
#1558 tx[6] = 1'b1;
#17 tx[6] = 1'b0;
end
initial begin
#1597 tx[7] = 1'b1;
#17 tx[7] = 1'b0;
end
initial begin
#37 precharge = 1'b1;
#11 precharge = 1'b0;
#27 precharge = 1'b1;
#11 precharge = 1'b0;
#333 precharge = 1'b1;
#11 precharge = 1'b0;
#38 precharge = 1'b1;
#11 precharge = 1'b0;
#27 precharge = 1'b1;
#11 precharge = 1'b0;
end
endmodule
If Generate Test Fixture Template on the Verilog HNL Netlisting Options form is set to Verimix,
the HNL testfixture files (
testfixture.template
and
testfixture.verimix
) are
automatically generated at netlisting time.
The testfixture.verimix File
The
testfixture.verimix
file is the stimulus file that is included by the
testfixture.template
file. The stimulus file is kept separate to prevent overwriting when
the
testfixture.template
file is regenerated. Do not use OSS naming conventions in
the Verilog HNL
testfixture.verimix
file, because name mapping is not used on the
testfixture.verimix
file, unlike with the FNL
testfixture.template
file. Use
Verilog design names directly in the
testfixture.verimix
file.
Testfixture files cannot be shared between FNL and HNL. The formats of the files are not
compatible.
To switch from HNL to FNL using the same simulation directory, replace the HNL
testfixture.template
with the FNL
testfixture.template
.
Summary :
Cadence Mixed-Signal Circuit Design Environment User Guide Running a Mixed-Signal Simulation October 2003 174 Product Version 5.0 end initial begin #2418 tx[3] = 1'b1; The testfixture.verimix File The testfixture.verimix file is the stimulus file that is included by the testfixture.template file.
Tags :
1b1,1b0,testfixtureerimix,testfixturetemplate,hnl,end,fnl,begin,initial,erilog,files,tx6,use