Cadence Mixed-Signal Circuit Design Environment User Guide
Running a Mixed-Signal Simulation
October 2003
175
Product Version 5.0
To switch from FNL to HNL using the same simulation directory, the HNL
testfixture.template
and
testfixture.verimix
files are created automatically.
Edit the
testfixture.verimix
file to provide the necessary stimulus.
The following example shows a hierarchical
testfixture.template
file.
`timescale 1ns / 1ns
module test;
wire out;
integer dc_mode_flag;
integer output_change_count;
integer max_dc_iter;
integer dc_iterations;
time vmx_time_offset;
pulledIE2Top top(out);
`define verimix
`ifdef verimix
//vms and dc iteration loop definitions
`include "IE.verimix"
//please enter any additional stimulus
//in the testfixture.verimix file
`include "testfixture.verimix"
//$save_waveform definitions
`include "saveDefs"
`endif
In HNL mode, the
testfixture.verimix
file must conform strictly to the Verilog
Integration standard for stimulus files. Instance and net name mapping macros such as [$]
and [#] are not allowed. You can access or drive any instance or net in the design hierarchy
because Verilog allows out-of-context reference to instances and nets embedded within
lower-level modules of the design hierarchy.
Note: You cannot use a digital stimulus to provide input directly to an analog gate. In this
case, use a stimulus block.
To create or edit a
testfixture.verimix
file
1. Choose Setup Stimulus Edit Digital.
A text editor window opens so you can edit the current
testfixture.verimix
file.
2. Make any stimulus changes necessary for this simulation.
The information in these files must be in Verilog Integration format. Refer to the raw
netlist file from your design for signal and instance names in Verilog namespace. Refer
to the Verilog-XL Integration for Composer Reference Manual for more information
about Verilog stimulus information and syntax.