Cadence Mixed-Signal Circuit Design Environment User Guide
Form Field Descriptions
October 2003
205
Product Version 5.0
s
N runs Spectre with the
-spp
option, which does not run the SPICE netlist reader on the
input file.
Include/Stimulus File Syntax specifies the syntax of an include or stimulus file. If a single
include or update file is being used, the syntax of the simulator is used. If two levels of files
are being used (the first in cdsSpice syntax and the second in native simulator syntax), only
cdsSpice is specified in this field.
simulator
Include File specifies a file containing circuit description information to be
included in the netlist.
simulator
Stimulus File specifies a special analog stimulus file.
Generate Map File specifies whether to generate a node map file. This file maps the
schematic names of nets to names used by the simulators in text format.
Mixed Signal Netlist Mode specifies whether a flat or hierarchical netlist is created. The
default is a flat netlist.
Output Format specifies the format of the simulation output data. You can select AWD, for
compatibility with the AWD display tool, or SignalScan, for compatibility with the SignalScan
tool. The default is AWD.
Verilog Netlist Options displays either the Flat Netlist Options form or the Hierarchical
Netlist Options form.
IE Default Options Form
Default IE Library Name is the default library name of the interface element models in this
design.
Default IE Model Name is the default cell name of the interface element models in this
design.
Detailed IE Generation controls the selection between detailed and nondetailed IE
generation modes.
Note: The initial settings in this form come from the SKILL variables
mspDefaultIELibName
,
mspDefaultIEModel
, and
mspGenerateDetailedIEFlag
in
the
./.cdsinit
file or
~/.cdsinit
file, or in the
./.simrc
file or
~/.simrc
file if no
.cdsinit
file is found. The
settings are then stored in the configuration file created by the hierarchy editor (HED).