Cadence Mixed-Signal Circuit Design Environment User Guide
Form Field Descriptions
Product Version 5.0
Cell Name is the master cell name for this instance. You cannot edit this field.
Instances is the name of the selected instance. You cannot edit this field.
Netlist Directory is the directory in which to put the netlist. If this directory does not exist, it
is created and initialized as a standard Verilog®-XL run directory.
Simulator specifies the simulator for netlisting.
Mixed Signal Options Form
DC Interval is the interval over which Verilog-XL simulates for each DC iteration.
Max DC Iter is the maximum number of iterations that the DC-relaxation loop is
Ignore turns off delay calculation. Use this setting if you are using a third-party
Estimate (Pre-Layout) uses Pearl to calculate prelayout digital delay estimates from
the schematic. For more information about this option, see the Setting Up for Pre-Layout
Use Existing (Layout) calculates delays from layout parasitics. For more information
about this option, see the Setting Up the Mixed-Signal Simulation Options.
Partition Display Form
Name lists the names of the partitions (analog, digital, mixed, unknown). Each name has its
own toggle that you can use to enable or disable the display of associated partitions. You can
change the colors for each partition by clicking on the Probe Layer and selecting the color you
Probe Layer lists the probe layers associated with each partition. The cyclic fields beside
each partition name let you change the default.
Note: The initial Probe Layer settings come from the SKILL variable
file, or in the
file if no
file is found. The settings are then stored in the
configuration file created by the HED.