Cadence Mixed-Signal Circuit Design Environment User Guide
Form Field Descriptions
Product Version 5.0
Cells that do not have the Lai_verilog or lmsi_verilog view type are netlisted according to
the priorities established with the Netlist These Views and Stop Netlisting at Views
Generate Test Fixture Template specifies whether the
regenerated and which Verilog
application is generated during
None generates a
file format useful for digital-only
simulations outside of the mixed-signal environment.
Verimix generates a
file format useful for Verimix (mixed-
Overwrite Verimix Stimulus overwrites any existing Verimix stimulus file.
Netlist Uppercase converts the netlist to uppercase. This option creates compatible
modules that are disparate in case.
Generate Pin Map creates the pin mapping files necessary to convert Standard Delay Files
(SDF) pin names to Verilog-XL pin names. Select this option only when you are ready to
This option is required when the pin names for a symbol in your schematic differ from those
in the Verilog library model description. After you create your pin map, your entire design is
netlisted automatically to ensure that the netlister creates pin maps for the entire design.
The Generate Pin Map option must remain selected on subsequent runs.
Otherwise, the netlister deletes your pin map directory.
Preserve Buses Preserves buses (vectors) in the resulting netlist. If this option is off, the
netlister expands vector nets to single-bit equivalents (scalars) in the resulting netlist.
Bus constructs that cannot be represented with Verilog bus constructs are represented by
using in-line concatenation, a Verilog feature. In some cases, bus names that are bundled or
that are part of aliasing schemes are mapped to new names because Verilog-XL does not
support certain bundling schemes. Mapped bus names are prefixed by
and have a
sequence number assigned. The sequence number is a function of how many names are
mapped, as shown below:
bus <a,b> maps to cdsbus<[0:1]> with a as bit 0 and b as bit 1
bus <0:8:2> maps to cdsbus1<0:4>