Cadence Mixed-Signal Circuit Design Environment User Guide
Form Field Descriptions
Product Version 5.0
Netlist SwitchRC includes user-defined RC switch properties when you run the netlister.
Skip Null Port ignores floating instance ports when you run the netlister.
Netlist Uselib uses the
directive to distinguish between two similarly named cells
from two different libraries rather than mapping the two cells to different Verilog module
Drop Port Range prints the module port without the port range.
Incremental Config List specifies that only those cellviews in the design that must be
renetlisted are included in the Netlist Configuration List.
Symbol Implicit suppresses printing of the net name during instance port formatting.
Assign For Alias specifies that the netlister uses an assignment statement for patches
between nets. Otherwise, the netlister applies the default
to patches between
Skip Timing Information causes the netlister to ignore timing information assigned to
instances in the design.
Declare Global Locally lets you declare global signals locally. Otherwise, the netlister uses
the default signals (Global Power Nets and Global Ground Nets).
Netlist Explicitly specifies that the netlister uses the pin name method instead of the pin
order method when printing the connectivity of instances. See Explicit Netlisting (Digital) on
page 113 for more information about using this option.
Support Escape Names causes the netlister to include escaped names in the netlist.
Support VHDLImport allows netlisting of VHDL Import modules.
Global Power Nets specifies the global net names you want netlisted with the supply1 wire
type. Supply1 wire types are driven to logic state 1. The net names you specify must conform
to global naming conventions as described in the Virtuoso Schematic Composer User
Global Ground Nets specifies the global net names you want netlisted with the supply0
wire type. Supply0 wire types are driven to logic state 0. The net names you specify must
conform to global naming conventions as described in the Virtuoso Schematic Composer
Global TimeScale Overwrite Schematic TimeScale specifies that the defined Global
Time Scale values (Global Sim Time and Global Sim Precision) overwrite any time values