CPLD Schematic Design Guide
5,790,882; 5,795,068; 5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548; 5,811,985; 5,815,004; 5,815,016;
5,815,404; 5,815,405; 5,818,255; 5,818,730; 5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230;
5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845; 5,831,907; 5,835,402; 5,838,167; 5,838,901;
5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577; 5,847,579; 5,847,580;
5,847,993; 5,852,323; Re. 34,363, Re. 34,444, and Re. 34,808. Other U.S. and foreign patents pending. Xilinx,
Inc. does not represent that devices shown or products described herein are free from patent infringement or from
any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise
any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or
correctness of any engineering or software support or assistance provided to a user.
Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in
such applications without the written consent of the appropriate Xilinx officer is prohibited.
Copyright 1991-1999 Xilinx, Inc. All Rights Reserved.