CPLD Schematic Design Guide
1-4
Xilinx Development System
Schematic Design Flow Example
This section runs through the entire schematic design process, from
creating a design to programming and simulating the design. The
following device-independent design, a 4-bit Johnson counter, is used
as an example:
Figure 1-2
Example 4-Bit Johnson Counter Design
Simulation results for this design are shown in the "Example View-
logic Functional Simulation Results" figure.
The design entry and simulation steps are summarized for Viewlogic
and Mentor software. Other supported schematic design software
Q
CLR
D
Q3B
FDCE
C
CE
OBUF
INV
IBUF
IBUF
IBUF
Q0
OPAD
X4863
Q
CLR
D
FDCE
C
CE
OBUF
Q1
OPAD
Q
CLR
D
FDCE
C
CE
OBUF
Q2
OPAD
IPAD
Q
CLR
D
FDCE
C
CE
CE
IPAD
C
IPAD
CLR
OBUF
Q3
OPAD
Summary :
CPLD Schematic Design Guide 1-4 Xilinx Development System Schematic Design Flow Example This section runs through the entire schematic design process, from creating a design to programming and simulating the design.
Tags :
clr,fdce,schematic,obuf,example,opad,simulation,ibuf,ipad,4bit,counter,figure,results