CPLD Schematic Design Guide
1-8
Xilinx Development System
schematic. In most libraries, models for all registered symbols contain
a global signal named PRLD which, when pulsed high, initializes all
the flip-flops inside the symbol's model. Remember to pulse the
PRLD signal high and drive all your top-level input signals (pins) to
valid logic levels before running your simulation vectors.
Viewlogic
If you are using Viewlogic, Xilinx provides a Viewsim command file
for the jcount design that can be found in installation_path/viewlog/
tutorial/jcount/jcount.cmd. The JCOUNT design is simulated using
the following Viewsim commands:
vector Q Q[3:0]
wave jcount.wfm CLK CE CLR Q
clock c 1 0
step 50ns
h prld
h CE
l CLR
cycle
l prld
cycle 5
l CE
cycle 2
h CE
cycle 5
h CLR
cycle 2
l CLR
cycle 3
The wave command automatically invokes a ViewTrace window
which displays the input and output simulation waveforms graphi-
cally.
Mentor
You can functionally simulate XNF or EDIF based designs by using
pld_xnf2sim
or
pld_edif2sim
to convert the designs to a Mentor
simulation model. The EDIF design must be Xilinx compatible and
expressed in Unified Library components.
Performing functional simulation on a pure schematic design consists
of creating a viewpoint in
pld_dve
from the schematic that you
Summary :
The JCOUNT design is simulated using the following Viewsim commands: vector Q Q[3:0] wave jcount.wfm CLK CE CLR Q clock c 1 0 step 50ns h prld h CE l CLR cycle l prld cycle 5 l CE cycle 2 h CE cycle 5 h CLR cycle 2 l CLR cycle 3 The wave command automatically invokes a ViewTrace window which displays the input and output simulation waveforms graphi- cally.
Tags :
cycle,design,prld,clr,schematic,simulation,xilinx,all,using,high,jcount,input,command