Getting Started with Schematic Design
CPLD Schematic Design Guide
1-11
Examining the Reports
Examine the reports to verify that the design was implemented as
you expected. The following report files (plain text) are automatically
produced by the fitter. If you are using a Design Manager you may
select a report from the report browser as follows:
Utilities
Report Browser
or select the report browser icon. The following reports are most
useful for schematic designs:
Figure 1-4
Report Browser
·
Fitter Report (jcount.rpt)- The fitter report shows the device
resources used by the design, how the external nets in your
design were mapped to the device pins, and the physical alloca-
tion of all device resources.
·
Timing Report (jcount.tim) - A timing summary report shows the
calculated worst-case timing for the logic paths in your design.
Performing Timing Simulation
To perform timing simulation you must extract a new EDIF netlist
from the implemented design. To avoid overwriting, you may want
to specify and output filename different than your design entry
netlist.
The Design Manager optionally produces timing simulation data
when you implement your design.
1.
To produce timing data go to the options menu:
Design
Implement
2.
The
Implementation
menu will appear. Click once on the
Options
key to get the
Options
dialog box.
Summary :
Getting Started with Schematic Design CPLD Schematic Design Guide 1-11 Examining the Reports Examine the reports to verify that the design was implemented as you expected. The following reports are most useful for schematic designs: Figure 1-4 Report Browser · Fitter Report (jcount.rpt)- The fitter report shows the device resources used by the design, how the external nets in your design were mapped to the device pins, and the physical alloca- tion of all device resources.
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timing,browser,reports,options,fitter,schematic,deice,simulation,select,shows,following,resources,manager