CPLD Schematic Design Guide
Xilinx Development System
dialog box appears. For more detailed infor-
mation on the dialog box options, refer to the Mentor Graphics
In the Design field, enter the name of the top-level design created
In the Select Desired Mode field, select
Normally, you select cross-probing for back-end EDDM designs
but not for front-end designs. You can only cross-probe back-end
designs that contain either pure schematic or schematics that
contain EDDM hierarchical models. You cannot cross-probe
designs written in HDL or that contain HDL models.
In order for cross-probing to work, other sessions of Design
Viewpoint Editor and QuickSim must be closed. Otherwise, the inter-
process communication gets confused. This includes another user's
session invoked by rlogin from another workstation.
Set the timing modes as desired.
now simulates the design. The QuickSim graph-
ical user interface appears. If you selected cross-probing, DVE is
invoked as well.
In DVE, open the viewpoint of the front-end schematic design,
that is, the viewpoint submitted to
Open the sheet of the design, and select signals that you wish to
These signals are automatically added to the QuickSim trace
window. If you have a file that sets up your trace window and
stimulus, use that instead. Any signals selected in the trace
window will select the same on the schematic on which they
reside in the DVE window. If such sheets have not been opened
in DVE yet, you must open them to see the selections.
The fitter automatically creates a JEDEC programming file, jcount.jed,
whenever a design is successfully implemented. Once you are satis-
fied with the results of the fitter (reports and timing simulation), you