CPLD Schematic Design Guide
Design Entry Techniques
This chapter discusses the fundamental techniques for expressing
logic in a schematic design for CPLDs. It concentrates mainly on the
symbols you place in your schematic and how you interconnect
them. It also explains how to retarget an existing schematic for an
FPGA design to a CPLD. This chapter includes the following sections:
"Retargeting a Design From a Different Family"
The Xilinx XC9000 library contains all component symbols used by
the Xilinx XC9500, XC9500XL, and XC9500XV device families. While
most symbols of the library are common to all families, there are
some symbols which are specific to CPLDs.
Physically, each major Xilinx device family (for example, 3000, 4000,
9000) has its own schematic library, implemented for each of the
supported schematic entry tools. For each tool, there is a library direc-
tory for the XC9000 device family, which supports XC9500,
XC9500XL, and XC9500XV devices. When a library component is
supported by multiple device families, its symbol appears in each of
the corresponding library directories.
When a component of the same name appears in multiple family
libraries, it has the same functionality and graphic symbol body, and
This chapter includes the following sections: · "Library Symbols" · "Input/Output Buffers" · "LogiBlox Modules" · "Behavioral Modules" · "Hierarchical Design" · "Retargeting a Design From a Different Family" Library Symbols The Xilinx XC9000 library contains all component symbols used by the Xilinx XC9500, XC9500XL, and XC9500XV device families.