Design Entry Techniques
CPLD Schematic Design Guide
2-5
To represent a bidirectional device I/O, use an OBUFE or OBUFT
whose output is connected to both an IOPAD symbol and to the input
of an IBUF, as shown in the "Bidirectional I/O Pin" figure.
Figure 2-1
Bidirectional I/O Pin
It is important that you label the nets that represent device input/
output pins in your design. These are the nets connecting between
IPAD and IBUF symbols, and between OBUF and OPAD symbols.
These names appear in the fitter reports as your pin names and are
used as signal names during simulation.
Note:
Do not use the reserved names "GND," "VCC," "PRLD" or
"MRESET" as labels for any nets or component instances in your
design.
Clock Inputs
To use a device input as a clock source, you can simply connect an
IBUF to the clock input of one or more flip-flops in your design. The
fitter automatically uses one of the global clock pins (GCK) of the
CPLD whenever possible.
A clock input signal may pass through an inverter to perform nega-
tive-edge clocking and the fitter can still use a global clock pin to
implement it. The same global clock input may even be used both
inverted and non-inverted to clock different flip-flops on opposite
edges of the clock signal, as shown in "Input CLK1 can be Optimized
onto a Global Clock Pin (GCK)" figure. Global clock inputs may also
be used as ordinary input signals to other logic elsewhere in the
design.
X4601
IBUF
OBUFE
IO3
IOPAD
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Summary :
Design Entry Techniques CPLD Schematic Design Guide 2-5 To represent a bidirectional device I/O, use an OBUFE or OBUFT whose output is connected to both an IOPAD symbol and to the input of an IBUF, as shown in the "Bidirectional I/O Pin" figure. X4601 IBUF OBUFE IO3 IOPAD · · · · · · · · · · · ·
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input,design,global,pin,names,use,ibuf,deice,figure,nets,fitter,signal,used