CPLD Schematic Design Guide
2-6
Xilinx Development System
Figure 2-2
Input CLK1 can be Optimized onto a Global Clock
Pin (GCK)
If a device input passes through any logic function (other than an
inverter) before it is used as a clock by any flip-flop, the input cannot
be routed using the global clock path. Instead, the clock signal will be
routed through the logic array for all flip-flops clocked by such a
device input.
There are a limited number of global clock pins on each CPLD device
(consult the device data sheet). If you need to explicitly control the
use of global clock pins, you can use the BUFG symbol in place of an
IBUF. You could alternatively apply the BUFG=CLK attribute to an
IBUF symbol or the pad net.
The global clock pins provide much shorter clock-to-output delays
than clocks routed through the logic array. Routing a clock through
the logic array also uses up one extra p-term for each flip-flop.
You can prevent the fitter from automatically mapping IBUF symbols
to the global clock pins.
1.
On the Design Manager graphical interface, go to the Flow
Engine and select
Setup
Options
2.
The Design Implementation Option menu appears. Select
Edit
Template
IBUF
D
D
Q
Q
f
IPAD
CLK1
X8058
Summary :
CPLD Schematic Design Guide 2-6 Xilinx Development System Figure 2-2 Input CLK1 can be Optimized onto a Global Clock Pin (GCK) If a device input passes through any logic function (other than an inverter) before it is used as a clock by any flip-flop, the input cannot be routed using the global clock path.
Tags :
clock,global,deice,logic,pins,input,ibuf,through,routed,design,array,clk1,select