CPLD Schematic Design Guide
Xilinx Development System
Go to a system command window that is properly configured to
run Viewlogic software. (The $path should include Viewlogic
software and the $WDIR variable should be properly set.) Your
current working directory should be your project directory
containing the designs to be converted.
Invoke the Viewlogic altran utility to automatically replace all
symbols in your design from the old library (XC3000) with corre-
sponding symbols from the new library (XC9000), as follows:
where old_library is the library alias of the device family from
which you are converting and new_library is the alias of your new
target library. For example:
altran -p design1 xc3000=xc9000
Processing a Design After Conversion
After converting a schematic from a different device family, perform
the following steps, as applicable:
Remove all attributes except INIT, FAST, SLOW, KEEP, BUFG,
FILE, NOREDUCE and timing specifications. Change the values
of PART, LOC, and PROHIBIT attributes as needed, or remove
In the Design Manager, create a new Xilinx project for the
converted schematic design.
a) From the Design Manager click the
menu and select
b) Enter a new project name to use for XC9000 implementation.
d) Before processing the design, open the Implementation
Options menus and select the options available for the new
When you perform either functional or timing simulation,
remember to pulse the PRLD signal High then Low. FPGA fami-
lies may use a GSR or GR signal for initialization.