Design Entry Techniques
CPLD Schematic Design Guide
If you wish to perform timing simulation, you may have to
change the internal nodes you drive and monitor. The CPLD
fitter optimizes the logic differently than FPGAs, which makes
many of the internal nodes in the design inaccessible. However,
all external signals are always visible.
The only schematic attributes common to FPGA devices and CPLD
Timing specifications for TIMESPEC and TIMEGRP symbols,
including TNM, PERIOD and OFFSET.
FAST and SLOW (output slew-rate control)
FILE=filename for behavioral modules
KEEP and COLLAPSE
The PART, LOC and PROHIBIT attributes are also used in a similar
way by other families, but you must change their values when you
Any attributes contained in the converted design which are not
supported by the target CPLD family should be removed from the
schematic before netlisting.
Converting Behavioral Modules
If your design contains behavioral modules, you may need to
perform some of these additional steps before running the fitter:
If your behavioral module contains state machine logic, you may
need to change the encoding style of the state machines. You
generally do not have to rewrite the logic, just the state assign-
ment. For FPGAs, which are rich in registers, one-hot encoding
using symbolic state representation is most efficient. For CPLDs,
which are rich in product terms, binary encoding (or other
encoding that minimizes state bits) is usually most efficient.
Conversion from one-hot encoding may be unnecessary for very
simple state machines.
If you are using a synthesis tool, recompile the behavioral
module specifying XC9000 as the target technology library.