Controlling Design Implementation
CPLD Schematic Design Guide
3-13
Multilevel Logic Optimization extracts combinatorial logic from your
design. Combinatorial logic includes:
·
register-to-register logic
·
path-to-register logic
·
register-to-path logic
·
path-to-path logic
Multilevel Logic Optimization operates on combinatorial logic
according to the following rules:
1.
If timespecs are set, the program will optimize for speed to meet
timespecs.
2.
If timespecs are not set, the program will optimize either for
speed or density, depending on the user setting of
Timing
Optimization
.
a) If
Timing Optimization
is turned on, the combinational
logic will be mapped for speed.
b) If
Timing Optimization
is turned off, the combinational
logic will be mapped for density. The goal of optimization
will then be to reduce th total number ot pterms.
3.
Logic marked with the attribute
NOREDUCE
will not be extracted
or optimized.
Setting Multilevel Logic Optimization
Multilevel Logic Optimization can be set from the
Advanced
tab of
the
Implementation Options
template of the Design Manager as
follows:
1.
Select
Design
Implement
2.
Press the
Options
softkey.
3.
Select
Edit Template
4.
Select the
Advanced
tab.
5.
Place a check in the
Use Multilevel Logic Optimization
box (the default is
On
).
Multilevel Logic Optimization will operate when you run the fitter.
Summary :
Controlling Design Implementation CPLD Schematic Design Guide 3-13 Multilevel Logic Optimization extracts combinatorial logic from your design. Combinatorial logic includes: · register-to-register logic · path-to-register logic · register-to-path logic · path-to-path logic Multilevel Logic Optimization operates on combinatorial logic according to the following rules: 1.
Tags :
multileel,design,select,speed,timing,timespecs,set,combinatorial,combinational,tab,mapped,options,implementation