CPLD Schematic Design Guide
3-26
Xilinx Development System
Figure 3-4
TNM on Macro Symbol
Placing TNMs on Nets or Pins to Group Flip-Flops
You can easily group flip-flops by flagging a common input net, typi-
cally either a clock net or an enable net. If you attach a TNM to a net
or load pin, that TNM applies to all flip-flops that are reached
through the net or pin. That is, that path is traced forward, through
any number of gates or buffers, until it reaches a flip-flop. That
element is added to the specified TNM group.
Placing a TNM on a net is equivalent to placing that TNM attribute
on every load pin of the net. Use pin TNM attributes when you need
finer control.
EN
D Q
EN
D Q
I
O
DI
DO
ADDRS
TNM=FFS:FLOPS;RAMS:MEM
WE
DI
DO
ADDRS
WE
Q5
Q4
Q3
Q2
Q1
Q0
EN
POS
PH0
PH1
PH2
PH3
NEG
X4678
Summary :
CPLD Schematic Design Guide 3-26 Xilinx Development System Figure 3-4 TNM on Macro Symbol Placing TNMs on Nets or Pins to Group Flip-Flops You can easily group flip-flops by flagging a common input net, typi- cally either a clock net or an enable net.
Tags :
tnm,net,pin,group,flipflops,placing,addrs,through,load,specified,xilinx,326,pos