Design Applications
CPLD Schematic Design Guide
4-3
Figure 4-2
Bidirectional Signals and Buses
Multiplexing Tristate Signals
Note:
XC9500 devices can emulate tristate bussing using special
gates that disable the macrocell feedback path to the FastCONNECT
matrix. XC9500XL and XC9500XV devices do not support internal
tristate buffers. Do not use BUFE or BUFT components in XC9500XL
or XC9500XV designs.
Three methods of multiplexing tristate signals are shown in the
"Methods of Multiplexing Tristate Signals" figure. Which method
you choose depends on your application, resources, and speed
requirements, although method C, which uses a multiplexer, is
usually best for CPLD designs.
X4851
OBUFE
E
IBUF
A
LOGIC
IOPAD
OBUFE
E
IBUF
B
A
A
B
LOGIC
IOPAD
OBUFE
E
IBUF
IOPAD
OBUFE8
E
E
A_OUT[7:0]
A_IN[7:0]
A[7:0]
B[7:0]
IBUF8
C
LOGIC
IOPAD8
IBUF8
B_IN[7:0]
B_OUT[7:0]
OBUFE8
IOPAD8
Summary :
Design Applications CPLD Schematic Design Guide 4-3 Figure 4-2 Bidirectional Signals and Buses Multiplexing Tristate Signals Note: XC9500 devices can emulate tristate bussing using special gates that disable the macrocell feedback path to the FastCONNECT matrix.
Tags :
tristate,signals,logic,multiplexing,obufe,ibuf,iopad,obufe8,cpld,xc9500x,methods,figure,iopad8