CPLD Schematic Design Guide
A-2
Xilinx Development System
Inputs to Global Nets -- BUFG
Applicable Elements
Input buffers (IBUF)
Description
Maps the tagged input buffers to a global net.
BUFG=CLK applied to an IBUF is equivalent to using a BUFG
symbol. BUFG=OE applied to an IBUF is equivalent to using a
BUFGTS symbol. BUFG=SR applied to an IBUF is equivalent to using
a BUFGSR symbol.
Syntax
BUFG={CLK | OE | SR }
where CLK, OE, and SR indicate clock, output enable, or set/reset,
respectively.
Schematic
Attached to an IBUF instance or the input pad net connected to an
IBUF input.
UCF/NCF file
Assign to an IBUF instance or the input pad net connected to an IBUF
input. This statement maps the signal named "clk1" to a global clock
net.
NET clk1 BUFG=CLK ;
Collapsing a Node -- COLLAPSE
Applicable Elements
Internal combinational logic nodes.
Description
Forces a node to be collapsed into all of its fanouts
Summary :
CPLD Schematic Design Guide A-2 Xilinx Development System Inputs to Global Nets -- BUFG Applicable Elements Input buffers (IBUF) Description Maps the tagged input buffers to a global net.
Tags :
ibuf,input,net,bufgclk,symbol,global,using,applied,equialent,bufg,applicable,pad,bufgsr