CPLD Schematic Design Guide
B-10
Xilinx Development System
* Primitive symbols (all others are macros)
Miscellaneous
GND*
Ground-connection signal tag
VCC*
VCC-connection signal tag
TIMEGRP*
Timing specification group table
TIMESPEC*
Timing requirement specification table
CONFIG*
Used to carry PART and PROHIBIT
attributes
Table B-2
LogiBLOX Modules
Module
Description
ACCUMULATOR Adds data to or subtracts it from the current
value stored in the accumulator register.
ADDER/
SUBTRACTER
Adds or subtracts two data inputs and a Carry
input.
CLOCK DIVIDER Generates a clock pulse whose period is a
multiple of the clock input period.
COMPARATOR
Compares the magnitude or equality of two
values.
CONSTANT
Forces a constant value onto a bus.
COUNTER
Generates a sequence of count values.
DATA REGISTER
Captures the input data on active Clock transi-
tions.
DECODER
Routes input data to 1-of-n lines on the output
port
INPUT/OUTPUT
Connects internal and external pin signals
MULTIPLEXER
Type 1, Type 2 -- Routes input data on 1-of-n
lines to the output port.
PAD
Simulates an input/output pad.
SHIFT REGISTER
Shifts the input data to the left or right.
Table B-1
CPLD Components
Component Name
Description/Features