CPLD Schematic Design Guide
C-6
Xilinx Development System
1.
Synopsys Design Compiler or FPGA Compiler netlist
(design_name.sxnf)
2.
Xilinx PLUSASM equation file (design_name.pld)
3.
XNF netlist (design_name.xnf)
4.
Synopsys Design/FPGA Compiler EDIF netlist
(design_name.sedif)
5.
EDIF netlist (design_name.edn, design_name.edf or
design_name.edif)
6.
Xilinx NGO (unexpanded) database file (design_name.ngo)
7.
Xilinx NGD (expanded) database file (design_name.ngd)
Fitter Options
The [options] field of the cpld command represents an optional list of
one or more command-line parameters. Invoking the
cpld
command with just the design name and no option parameters runs
the fitter with all default conditions, including automatic device
selection.
The following are the
cpld
command-line parameters that apply to
schematic design entry:
·
-autoslewpwr
-- reduces slew rate before reducing power
mode if
autopwrslew
is enabled.
·
-autopwrslew
-- reduces power mode and/or slew rate if
timespecs can still be met or if no timespecs apply.
·
-detail
-- produces a detailed path timing report
(design_name.tim) instead of the default summary report.
·
-grounds
-- creates programmable ground pins on unused I/
Os.
·
-ignoreloc
-- temporarily ignores all LOC attributes in the
schematic, allowing the fitter to assign the locations of all I/O
pins.
·
-ignorets
-- temporarily ignores all timing specification
attributes in the schematic.
·
-inputs
<n> -- maximum number of function block inputs
allowed as a result of logic collapsing. Default is 36.