CPLD Schematic Design Guide
Xilinx Development System
By default the simulation data is produced in EDIF format. Format is
set from the
dialog box; if you want to
select another format, go to the
tab and click the down
arrow adjacent to
then select from the supported formats.
When you implement the design, the Flow Engine produces timing
simulation data files. Each time the data is produced, it is automati-
cally exported to your design directory.
You can now use these files to simulate the design with a supported
third party simulation tool.
Simulation on Workstation Command LIne
the ability to simulate vhdl, verilog, and edif designs on a worksta-
tion command line. See the Development System Reference Guide for
instructions on using these three programs.
CPLD Schematic Design Guide D-2 Xilinx Development System Figure D-1 Options By default the simulation data is produced in EDIF format.