DESIGN FLOW OVERVIEW
9
are still described in VHDL and Verilog. Circuit simulators such as SPICE
and Spectre are used in the analog domain to analyze the behavior of the
designed block.
Based on the gate level or circuit netlist and data of the circuit technology
the layout of the circuit is designed. The design is now represented as
polygons at different layers of an integrated circuit. In the digital domain this
step is well-automated. The tools will check if the design rules for a
specified circuit technology are fulfilled. In the analog domain further
manual optimization of layout may be necessary, for example to minimize
crosstalk between signals or to achieve a symmetric design. Tools that
extract parasitic effects that originate from layout also support the layout
verification.
2.2
Top-down System Design
System Level
(Executable Specification)
Electrical Block Level
(digital: Register Transfer
Level)
Circuit / Transistor Level
(digital: Gate Level)
Layout Level
System Partitioning
(HW and SW)
Circuit Design
(Logic Synthese)
Layout Synthese
System Level Simulation
(CoCentric, Matlab, SPW,
partially VHDL-AMS)
Behavioral Simulation
(VHDL-AMS, Verilog-AMS,
SystemC)
Circuit Simulation
(VHDL-AMS, Spice,
Spectre)
Layout Simulation,
Parasitic Extraction
Design Levels
Simulation Support
(analog / mixed signal)
System
Specification
Analog/Digital
Mixed-Signal
Simulation
Circuit
Simulation
VHDL-AMS
coverage
Figure 2-2. Top-down design and simulation support
Summary :
2.2 Top-down System Design System Level (Executable Specification) Electrical Block Level (digital: Register Transfer Level) Circuit / Transistor Level (digital: Gate Level) Layout Level System Partitioning (HW and SW) Circuit Design (Logic Synthese) Layout Synthese System Level Simulation (CoCentric, Matlab, SPW, partially VHDL-AMS) Behavioral Simulation (VHDL-AMS, Verilog-AMS, SystemC) Circuit Simulation (VHDL-AMS, Spice, Spectre) Layout Simulation, Parasitic Extraction Design Levels Simulation Support (analog / mixed signal) System Specification Analog/Digital Mixed-Signal Simulation Circuit Simulation VHDL-AMS coverage Figure 2-2.
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simulation,design,leel,layout,system,hdlams,domain,analog,support,digital,gate,designed,tools