12 Chapter
2
At the beginning of the design, the system is described with some
algorithms. After implementation the system may consist of a large number
of transistors. Concept verification is needed to check that the
implementation meets the requirements of the system.
In the "V" diagram (Figure 2-5) the verification starts from the layout
level (bottom) and then proceeds up to the block and system levels.
After layout, simulation parasitic effects can be back-annotated into the
circuit netlist. The circuit simulation with the extracted netlist is used to
verify the circuit design. The designed circuits can now be combined into
functional blocks, which are checked against their specification in a block
level simulation. Finally the designed blocks can be connected to the system.
System level simulation verifies that the blocks fit into the system
environment.
It is recommended to start verification before the design is completed at
layout level. After each design step simulation can be used to verify the
design or component against the specification.
System Level
(Executable
Specification)
Implementation
Layout Verification,
Parasitic Extraction
Circuit Verification
Block Verification
System Verification
Layout Level
Circuit / Transistor
Level
Electrical Block
Level
Verification
Time
Time
Figure 2-5. Top -down design and bottom-up verification (V diagram)
Summary :
System Level (Executable Specification) Implementation Layout Verification, Parasitic Extraction Circuit Verification Block Verification System Verification Layout Level Circuit / Transistor Level Electrical Block Level Verification Time Time Figure 2-5.
Tags :
system,erification,leel,design,layout,circuit,simulation,block,after,implementation,specification,blocks,into