Structural description of the PLL circuit in VHDL-AMS
In order to simulate the PLL circuit these mathematical models have to
be translated into VHDL-AMS descriptions. At the beginning, we assume
that the models of the basic building blocks are available. We only have to
connect and parameterize them. The structural description can be done with
reference to the interface descriptions of the block models. The interfaces are
described in VHDL by the entity declarations. These declarations contain the
identifiers of the generic model parameters, their types, and optionally, their
default values. The connection points are summarized in the port list. The
declaration of a connection point characterizes an element of the port list. A
terminal, for instance, is a connection point in a network model.
Furthermore, identifiers and a characterization by type or nature belong to a
port declaration. In the case of an electrical network the nature is
The entity declaration of the voltage source model used is shown in the
following lines of code. The parameter WAVE describes the voltage
waveform as a list of times and values in a similar way as in any well-known
SPICE simulator [QNP93].
entity VPWL is
WAVE : REAL_VECTOR; -- time value pairs T1, V1, ...
-- units: [s] and [V]
ACMAG : REAL := 0.0; -- AC magnitude
ACPHASE : REAL := 0.0 -- AC phase
terminal P : ELECTRICAL; -- positive terminal
terminal N : ELECTRICAL -- negative terminal
end entity VPWL;
The VCO entity is declared in a similar way. The assert statement checks
whether model parameters are assigned in a correct way during instantiation.
entity VCO is
generic (F0 : REAL := 1.0; -- center frequency [Hz]
KF : REAL := 1.0; -- gain [Hz/V]
AMPL : REAL := 1.0; -- amplitude [V]
PHI0 : REAL := 0.0 -- initial phase [rad]
port (terminal INP : ELECTRICAL; -- input terminal
terminal OUTP : ELECTRICAL -- output terminal
assert F0 > 0.0 and KF > 0.0
report "F0 and KF > 0.0 required."
end entity VCO;