54 Chapter
6
because out is a reserved word. Reserved words are printed in boldface
letters in code segments in this chapter. A full list of reserved word can
be found in the 1076.1-1999 IEEE Standard VHDL Analog and Mixed-
Signal Extensions.
VHDL as well as VHDL-AMS are not case sensitive. Thus, for instance,
delay_time, DELAY_TIME, and Delay_Time are all the same. This is
also true for reserved words. For instance, entity, Entity and ENTITY
are considered the same.
Simple identifiers must start with an alphabetic letter followed by a letter,
a digit, or an underline character (`_'). Identifiers cannot end with an
underline character. Underline characters must be separated by a letter or
a digit. Some examples of legal identifiers are:
legal_identifier
node23
InputVoltage
Design unit architecture
An architecture associated with an entity declaration describes the
internal organization or operation of a design entity. An architecture
describes the behavior, data flow, or structure of a design entity. It can be
described using concurrent and simultaneous statements. Concurrent
statements describe digital time-discrete behavior. Simultaneous statements
describe analog time-continuous behavior. Concurrent statements are
known from digital VHDL. Simultaneous statements are new language
constructs in VHDL-AMS. Signals are the fundamental objects that carry
digital waveforms. Concurrent statements update the values of signals.
Quantities are the fundamental objects that carry analog waveforms.
Simultaneous statements define relationships between quantities. However,
quantities can be read in concurrent statements and signals can be read in
simultaneous statements. Thus, not only digital and analog behavior can be
expressed in VHDL-AMS, but the description of mixed-signal (analog-
digital) behavior is also possible. The order of concurrent and simultaneous
statements in an architectural body has no influence on the results of a
simulation.
In conclusion, a design entity is an entity declaration together with an
associated architecture body. Please keep in mind that a given entity
declaration may be shared by many design entities, each of which has a
different architecture.
Summary :
Some examples of legal identifiers are: legal_identifier node23 InputVoltage Design unit architecture An architecture associated with an entity declaration describes the internal organization or operation of a design entity. However, quantities can be read in concurrent statements and signals can be read in simultaneous statements. The order of concurrent and simultaneous statements in an architectural body has no influence on the results of a simulation.
Tags :
entity,simultaneous,concurrent,analog,digital,design,behaior,architecture,resered,hdl,delaytime,signals,identifiers