INTRODUCTION TO VHDL-AMS
107
use WORK.all;
entity BENCH is end entity BENCH;
architecture BENCH_PID of BENCH is
quantity INPUT, OUTPUT : REAL; -- connection points
begin
Q1: entity QPWL(BASIC)
generic map (WAVE =>
(0.0, 0.0, 1.0, 1.0, 2.0, 1.0, 4.0, -1.0, 5.0, -1.0,
6.0, 0.0, 10.0, 0.0))
port map (INPUT);
UUT: entity PID(IDEAL)
generic map (KR => 5.0, TN => 2.0, TV => 1.0)
port map (Q_IN => INPUT, Q_OUT => OUTPUT);
end architecture BENCH_PID;
Figure 6-50. Results of PID controller test (KR=5.0, TN=2.0, TV=1.0)
6.5
Mixed-Signal Simulation
A mixed-signal simulation must always be carried out if the system being
simulated includes both analog and digital parts. In VHDL-AMS analog and
digital behavior (simultaneous and concurrent statements, respectively) can
be described within the same architecture. You must consider:
Method of description to allow exchanging data between the analog and
the digital part of a model
An extended simulation cycle that takes into account the solving of
DAE's (differential algebraic equations but leaves the previous VHDL
simulation cycle untouched
Synchronization between analog and digital simulators due to different
time scales.
Summary :
You must consider: Method of description to allow exchanging data between the analog and the digital part of a model An extended simulation cycle that takes into account the solving of DAE's (differential algebraic equations but leaves the previous VHDL simulation cycle untouched Synchronization between analog and digital simulators due to different time scales.
Tags :
analog,digital,entity,simulation,map,input,bench,architecture,benchpid,between,end,cycle,output